High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection
High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection
by Anirban Sengupta
The Institution of Engineering and Technology, 2024 Cloth: 978-1-83724-117-0 | eISBN: 978-1-83724-340-2 (ePub) | eISBN: 978-1-83724-118-7 (PDF)
ABOUT THIS BOOK | TOC
ABOUT THIS BOOK
High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation.
TABLE OF CONTENTS
Chapter 1: Introduction to hardware security and trust and high-level synthesis
Chapter 2: High-level synthesis-based watermarking using protein molecular biometric with facial biometric encryption
Chapter 3: High-level synthesis-based watermarking using retinal biometrics
Chapter 4: HLS-based mathematical watermarks for hardware security and trust
Chapter 5: High-level synthesis-based watermarking using multimodal biometric
Chapter 6: High-level synthesis-based watermarking using crypto-chain signature framework
Chapter 7: HLS-based fingerprinting
Chapter 8: Hardware obfuscation-high level synthesis-based structural obfuscation for hardware security and trust