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This book presents advanced forensic detective control and obfuscation techniques for securing hardware IP cores by exploring beyond conventional technologies. The theme is important to researchers in various areas of specialization, because it encompasses the overlapping topics of EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and finally application specific processor/hardware accelerator design for consumer electronics applications.

Hardware trojans - which involve malicious modification of integrated circuits (ICs) during the design or fabrication stage - can give access to sensitive information, deny service, and so on. They can be difficult to detect but have serious consequences for the security of the IC.

High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation.

IP Core Protection and Hardware-Assisted Security for Consumer Electronics presents established and novel solutions for security and protection problems related to IP cores (especially those based on DSP/multimedia applications) in consumer electronics. The topic is important to researchers in various areas of specialization, encompassing overlapping topics such as EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and application specific processor/hardware accelerator design.

Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors presents state-of-the art explanations for detective control-based security and protection of digital signal processing (DSP) and machine learning coprocessors against hardware threats. Such threats include intellectual property (IP) abuse and misuse, for example, fraudulent claims of IP ownership and IP piracy. DSP coprocessors such as finite impulse response filters, image processing filters, discrete Fourier transform, and JPEG compression hardware are extensively utilized in several real-life applications. Further, machine learning coprocessors such as convolutional neural network (CNN) hardware IP cores play a vital role in several applications such as face recognition, medical imaging, autonomous driving, and biometric authentication, amongst others.

Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing, which are also optimised for performance and efficiency. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators for DSP, multimedia and image processing applications are explored.